1. Technical Field
This disclosure relates to semiconductor packages, and, more particularly, to a semiconductor package and an electronic package having the semiconductor package that have an increased yield.
2. Description of Related Art
With the rapid development of electronic industry, electronic products have more and more versatile, high-performance functionalities. A variety of die packages come to the market, including a die scale package (CSP), a flip-die packaging module, such as a direct die attached (DCA) module or multi-die module (MCM), and a 3D IC die stack module.
FIG. 1 is a cross-sectional view of a 3D IC semiconductor package 1 according to the prior art. A plurality of semiconductor dies 11 are disposed on a through silicon interposer (TSI) 10 via a plurality of solder bumps 110. An encapsulation layer 12 is formed on the through silicon interposer 10 to encapsulate the semiconductor die 11. The through silicon interposer 10 has a plurality of through-silicon vias (TSVs) 100, and a distribution layer (RDL) 101 formed on the TSVs 100 and electrically connected to the solder bumps 110. The through silicon interposer 10 is coupled via the through-silicon vias 100 and a plurality of conductive elements 130 to a packaging substrate 13. An underfill 14 encapsulates the conductive elements 130.
In the semiconductor package 1, the through silicon interposer 10 has four right-angle corners, as shown in FIG. 1′. After the through silicon interposer 10 is packaged, greater die corner stresses will be formed at the corners due to stress concentration, and a strong stress will be formed between the through silicon interposer 10 and the encapsulation layer 12, as indicated by dashed circles S of FIG. 1′. Therefore, the through silicon interposer 10 is likely cracked along the four corners, or delaminated from the encapsulation layer 12 due to coefficient of thermal expansion (CTE) mismatch, i.e., a delamination problem. As a result, the through silicon interposer 10 cannot be electrically connected to the semiconductor die 11 effectively, or pass the reliability test, and has a poor product yield.
After the through silicon interposer 10 is packaged, a strong stress will also be formed among the four corners and the underfill 14, as indicated by dashed circles K of FIG. 1. As a result, the through silicon interposer 10 will be likely cracked along the four corners, or delaminated from the underfill 14, and also has a poor product yield.
Therefore, how to solve the above problems of the prior art is becoming the urgent issues in the art.